diff -bBdurNP u-boot-1.1.1/MAKEALL u-boot-1.1.1-gum/MAKEALL --- u-boot-1.1.1/MAKEALL 2004-04-18 16:32:11.000000000 -0700 +++ u-boot-1.1.1-gum/MAKEALL 2004-07-19 13:59:04.966845618 -0700 @@ -147,7 +147,7 @@ ## Xscale Systems ######################################################################### -LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250" +LIST_pxa="cradle csb226 innokom gumstik lubbock wepep250 xm250" LIST_ixp="ixdp425" diff -bBdurNP u-boot-1.1.1/Makefile u-boot-1.1.1-gum/Makefile --- u-boot-1.1.1/Makefile 2004-04-24 16:23:30.000000000 -0700 +++ u-boot-1.1.1-gum/Makefile 2004-07-19 13:59:04.967845441 -0700 @@ -121,7 +121,6 @@ # The "tools" are needed early, so put this first # Don't include stuff already done in $(LIBS) SUBDIRS = tools \ - examples \ post \ post/cpu .PHONY : $(SUBDIRS) @@ -1078,6 +1077,9 @@ csb226_config : unconfig @./mkconfig $(@:_config=) arm pxa csb226 +gumstik_config : unconfig + @./mkconfig $(@:_config=) arm pxa gumstik + innokom_config : unconfig @./mkconfig $(@:_config=) arm pxa innokom diff -bBdurNP u-boot-1.1.1/board/gumstik/Makefile u-boot-1.1.1-gum/board/gumstik/Makefile --- u-boot-1.1.1/board/gumstik/Makefile 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-1.1.1-gum/board/gumstik/Makefile 2004-07-19 13:59:04.967845441 -0700 @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := gumstik.o flash.o +SOBJS := memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff -bBdurNP u-boot-1.1.1/board/gumstik/config.mk u-boot-1.1.1-gum/board/gumstik/config.mk --- u-boot-1.1.1/board/gumstik/config.mk 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-1.1.1-gum/board/gumstik/config.mk 2004-07-19 13:59:04.968845265 -0700 @@ -0,0 +1,11 @@ +# +# This is config used for compilation of WEP EP250 sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +# + +TEXT_BASE = 0xA3F00000 +#TEXT_BASE = 0x00000000 diff -bBdurNP u-boot-1.1.1/board/gumstik/early_refresh.S u-boot-1.1.1-gum/board/gumstik/early_refresh.S --- u-boot-1.1.1/board/gumstik/early_refresh.S 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-1.1.1-gum/board/gumstik/early_refresh.S 2004-07-19 13:59:04.968845265 -0700 @@ -0,0 +1,50 @@ +#define COTULLA_CP15_B1_VAL 0x69052903 + /* Workaround for early termination of SDRAM autorefresh on exit from + processor's sleep state in B1 stepping of XPA250/210. (sighting 27004) + Need first forced refresh within 8 usec. + + - Code snippet received from validation team, slightly modified + + Notes: - MMU assumed to be inactive at this time, so use physical addresses + - Eboot didn't boot on A1 stepping without the leading exclusion, + so the core code must be restricted to B1 only. + */ + + mrc p15, 0, r9, c0, c0, 0 @ Grab CPU ID + ldr r3, =COTULLA_CP15_B1_VAL @ Load the B1 CPU ID value + cmp r9, r3 + bne EARLY_REFRESH_DONE + + @ Eboot loads BIN image into RAM, + @ turns off the MMU and then jumps here. + @ If we're already executing from RAM, don't mess with it + + mov r0, #0x400000 @ Just at the end of boot device addressing space + cmp r0, pc @ Are we executing from boot flash space? + bls EARLY_REFRESH_DONE @ if outside that space, skip this. + + + /* + Need to set MDREFR:DRI field to 0 for this to work. Side effect is + picking the MEMCLK:SDCLK ratio. The specified value (0x038FF000) + sets that ratio as 2:1. + This corresponds to the defaults after reset, including sleep reset. + 0x038ff000 == MDREFR_K2FREE | MDREFR_K1FREE | MDREFR_K0FREE | + MDREFR_K2DB2 | MDREFR_K2RUN | + MDREFR_K1DB2 | MDREFR_K1RUN | MDREFR_E1PIN | + MDREFR_K0DB2 | MDREFR_K0RUN | MDREFR_E0PIN + */ + + ldr r0, =0X48000004 @ Memory controller base physical addr+ REFR Offset. + mov r1, #0x03800000 + orr r1, r1, #0x000FF000 + str r1, [r0] + + mov r0, #CFG_DRAM_BASE + ldr r1, [r0] @ CAUSES the 1st row refresh to all partitions + mov r2, #0x2000 @ 8k loo +1: + ldr r1, [r0] @ CAUSES a row refresh to all partitions + subs r2, r2, #0x1 + bpl 1b @ while >= 0 +EARLY_REFRESH_DONE: diff -bBdurNP u-boot-1.1.1/board/gumstik/flash.c u-boot-1.1.1-gum/board/gumstik/flash.c --- u-boot-1.1.1/board/gumstik/flash.c 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-1.1.1-gum/board/gumstik/flash.c 2004-07-19 13:59:04.974844205 -0700 @@ -0,0 +1,460 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "intel.h" + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH16 +#undef FLASH_PORT_WIDTH32 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define flash_poke(ad,hw) asm volatile ("strh %[halfword],%[addr]\nnop" : : [halfword] "r" (hw), [addr] "m" (*ad) : "memory") +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPWV *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0] ); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf (CFI_CHIPN_INTEL_28F128J3A "\n"); + break; + case FLASH_28F320J3A: + printf (CFI_CHIPN_INTEL_28F320J3A "\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + FPW manufacturer, chip; + + /* Write auto select command: read Manufacturer ID */ + flash_poke(addr, CFI_INTEL_CMD_READ_IDENTIFIER); + + manufacturer = addr[CFI_MANUFACTURER_CODE_ADDRESS]; + chip = addr[CFI_DEVICE_CODE_ADDRESS]; + + switch (manufacturer) { + + case (FPW) CFI_MANUFACTURER_INTEL: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + flash_poke(addr,CFI_INTEL_CMD_READ_ARRAY); /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (chip) { + + case (FPW) CFI_CHIP_INTEL_28F320J3A: + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + flash_poke(addr,CFI_INTEL_CMD_READ_ARRAY); /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPW *) (info->start[sect]); + FPW status; + + printf("Erasing sector %d at %08lx...",sect,addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + flash_poke(addr, CFI_INTEL_CMD_BLOCK_ERASE); /* erase setup */ + flash_poke(addr, CFI_INTEL_CMD_CONFIRM); /* erase confirm */ + + while (((status = *addr) & CFI_INTEL_SR_READY) != CFI_INTEL_SR_READY) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + flash_poke(addr, CFI_INTEL_CMD_SUSPEND); /* suspend erase */ + while(((status = *addr) & CFI_INTEL_SR_READY) != CFI_INTEL_SR_READY); + if(status & CFI_INTEL_SR_ERASE_SUSPEND == CFI_INTEL_SR_ERASE_SUSPEND) + { + printf("Erase suspended.\n"); + } + else + { + printf("Erase completed\n"); + } + rcode = 1; + break; + } + } + + if((status & CFI_INTEL_SR_ERASE_ERROR) == CFI_INTEL_SR_ERASE_ERROR) { + printf("Got an error in flash erase!\n"); + flash_poke(addr, CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + } + else + { + printf("done\n"); + } + + flash_poke(addr, CFI_INTEL_CMD_READ_ARRAY); /* reset to read mode */ + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + flash_poke(addr, CFI_INTEL_CMD_PROGRAM1); /* write setup */ + flash_poke(addr, data); /* actual write */ + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & CFI_INTEL_SR_READY) != CFI_INTEL_SR_READY) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + printf("timeout writing %08lx\n",addr); + flash_poke(addr, CFI_INTEL_CMD_SUSPEND); + while(!((status = *addr) & CFI_INTEL_SR_READY)); + flash_poke(addr, CFI_INTEL_CMD_READ_ARRAY); + return (1); + } + } + + if(status & CFI_INTEL_SR_PROGRAM_ERROR) + { + if(status & CFI_INTEL_SR_BLOCK_LOCKED) + { + printf("Block locked error writing %08lx\n",addr); + } + else if(status & CFI_INTEL_SR_PROGRAM_ERROR) + { + printf("Program error writing %08lx\n",addr); + } + else + { + printf("Miscellaneous error writing %08lx\n",addr); + } + flash_poke(addr, CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + flash_poke(addr, CFI_INTEL_CMD_READ_ARRAY); + return 1; + } + + flash_poke(addr, CFI_INTEL_CMD_READ_ARRAY); + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff -bBdurNP u-boot-1.1.1/board/gumstik/gumstik.c u-boot-1.1.1-gum/board/gumstik/gumstik.c --- u-boot-1.1.1/board/gumstik/gumstik.c 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-1.1.1-gum/board/gumstik/gumstik.c 2004-07-20 16:09:07.886303005 -0700 @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#include +#include + +int board_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = 373; + gd->bd->bi_boot_params = 0xa0000100; + +/* + * Setup GPIO stuff to get serial working + */ +#if defined( CONFIG_FFUART ) + GPDR1 = 0x80; + GAFR1_L = 0x8010; +#elif defined( CONFIG_BTUART ) + GPDR1 = 0x800; + GAFR1_L = 0x900000; +#endif + PSSR = 0x20; + + return 0; +} + +int dram_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + +#if ( CONFIG_NR_DRAM_BANKS > 0 ) + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 1 ) + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 2 ) + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 3 ) + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; +#endif + + return 0; +} + diff -bBdurNP u-boot-1.1.1/board/gumstik/intel.h u-boot-1.1.1-gum/board/gumstik/intel.h --- u-boot-1.1.1/board/gumstik/intel.h 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-1.1.1-gum/board/gumstik/intel.h 2004-07-19 13:59:04.970844911 -0700 @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2002 ETC s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Marcel Telka , 2002. + * + * Documentation: + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + */ + +#ifndef FLASH_INTEL_H +#define FLASH_INTEL_H + +#include + +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ + +#define CFI_INTEL_CMD_READ_ARRAY 0x00FF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x0090 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_QUERY 0x0098 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x0070 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x0050 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM1 0x0040 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM2 0x0010 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0x00E8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CONFIRM 0x00D0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_BLOCK_ERASE 0x0020 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_SUSPEND 0x00B0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_RESUME 0x00D0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_SETUP 0x0060 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_BLOCK 0x0001 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0x00D0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x002F /* 28FxxxK3, 28FxxxK18 */ + +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ + +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ + +#define CFI_MANUFACTURER_CODE_ADDRESS 0x00 /* Address of the manufacturer code */ +#define CFI_DEVICE_CODE_ADDRESS 0x01 /* Address of the device code */ + +/* Intel flash manufacturer code - see Table 17. in [1] */ + +#define CFI_MANUFACTURER_INTEL 0x0089 +#define CFI_MANUFACTURERN_INTEL "Intel" + +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ + +#define CFI_CHIP_INTEL_28F320J3A 0x0016 +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" +#define CFI_CHIP_INTEL_28F640J3A 0x0017 +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" +#define CFI_CHIP_INTEL_28F128J3A 0x0018 +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" +#define CFI_CHIP_INTEL_28F256J3C 0x001D +#define CFI_CHIPN_INTEL_28F256J3C "28F256J3C" + +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ + +#define CFI_CHIP_INTEL_28F640K3 0x8801 +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" +#define CFI_CHIP_INTEL_28F128K3 0x8802 +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" +#define CFI_CHIP_INTEL_28F256K3 0x8803 +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" +#define CFI_CHIP_INTEL_28F640K18 0x8805 +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" +#define CFI_CHIP_INTEL_28F128K18 0x8806 +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" +#define CFI_CHIP_INTEL_28F256K18 0x8807 +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" + +#endif /* FLASH_INTEL_H */ + diff -bBdurNP u-boot-1.1.1/board/gumstik/memsetup.S u-boot-1.1.1-gum/board/gumstik/memsetup.S --- u-boot-1.1.1/board/gumstik/memsetup.S 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-1.1.1-gum/board/gumstik/memsetup.S 2004-07-20 16:13:17.987139448 -0700 @@ -0,0 +1,212 @@ +#include +#include +#include + + +.macro CPWAIT + mrc p15,0,r0,c2,c0,0 + mov r0,r0 + sub pc,pc,#4 +.endm + + +.globl memsetup +memsetup: + + + cmp pc, #0xa0000000 /** test if we're in SDRAM **/ + bhi end_of_memsetup /** if we are, then jump **/ + + /* First, setup GPIOs */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + + /* The procedure below uses sample code generated by the Intel PXA250 Memory + * Configuration Tool [http://appzone.intel.com/pcg/pxa250/memory/] which has + * then been modified manually while following the documentation in + * "Intel PXA255 Process Developer's Manual" [order #278693-002] + * Chapter 6.11 - Hardware, Watchdog, or Sleep Reset Operation */ + + /* Step 1: After hardware reset, complete a power-on wait of 200us to allow clocks to stabilize */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */ +10: + ldr r2, [r3] + cmp r4, r2 + bgt 10b + + /* Step 1a: Write MSC0, MSC1, MSC2 */ + ldr r3, =MSC0 /* Configures /CS0 and /CS1 */ + ldr r2, =0x0000A5BB /* Generated value */ + str r2, [r3] + ldr r2, [r3] /* the MSC register should be read after it is written with */ + /* a new value before an access to the memory is attempted. */ + /* (see MSC section of manual) */ + + /* Step 1b: Write MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1 (Skip on gumstix) */ + /* Step 1c: Write MDREFR:K0RUN and MDREFR:E0PIN. Configure MDREFR:K0DB2. Retain + * the current values of MDREFR:APD and MDREFR:SLFRSH. MDREFR:DRI must + * contain a valid value. Deassert MDREFR:KxFREE. (Skip on gumstix) */ + + ldr r3, =MDREFR + ldr r2, [r3] /* read MDREFR value */ + str r2, [r3] /* configure K2DB1 and K2DB2 */ + + ldr r1, =0xfff + bic r2, r2, r1 /* Clear DRI -- INTEL TOOL LEAVES THIS STEP OUT!! */ + orr r2, r2, #0x018 /* configure a valid SDRAM Refresh Interval (DRI) */ + str r2, [r3] + + /* Step 2: Configure Synchronous Static memory (Skip on gumstix) */ + + /* Step 4: In systems that contain SDRAM, transition the SDRAM controller through the following state sequence: + * a. self-refresh + * b. power-down + * c. PWRDNX + * d. NOP */ + + orr r2, r2, #0x00010000 /* assert K1RUN for SDCLK1 */ + str r2, [r3] /* change from "self-refresh and clock-stop" to "self-refresh" state */ + + bic r2, r2, #0x00400000 /* clear SLFRSH bit field */ + str r2, [r3] /* change from "self-refresh" to "Power-down" state */ + + orr r2, r2, #0x00008000 /* set the E1PIN bit field */ + str r2, [r3] /* change from "Power-down" to "PWRDNX" state */ + + nop /* no action is required to change from "PWRDNX" to "NOP" state */ + + /* Step 4f: Write MDCNFG (with enable bits deasserted), MDCNFG:DE3:2,1:0 set to 0. */ + + ldr r3, =MDCNFG /* Load the SDRAM Configuration register. Must not be enabled yet. */ + ldr r2, =0x000019C8 /* Value from Intel tool */ + str r2, [r3] /* Write to MDCNFG register */ + + /* Step 5: For systems that contain SDRAM, wait a specified NOP power-up waiting period required by + * the SDRAMs to ensure the SDRAMs receive a stable clock with a NOP condition */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */ +20: + ldr r2, [r3] + cmp r4, r2 + bgt 20b + + /* Step 6: Ensure the data cache is disabled -- should not be needed out of reset, but best to be safe*/ + + mov r0, #0x78 /* turn everything off */ + mcr p15, 0, r0, c1, c0, 0 /* caches off, MMU off, etc. */ + + CPWAIT /* wait for co-processor */ + + /* Step 7: On a hardware reset in systems that contain SDRAM, trigger the specified number (typically + eight) of refresh cycles by attempting non-burst read or write accesses to any disabled + SDRAM bank. Each such access causes a simultaneous CBR refresh cycles for all four banks, + which causes a pass through the CBR state and back to NOP. On the first pass, the PALL state + occurs before the CBR state. */ + + ldr r3, =PHYS_SDRAM_1 + mov r2, #9 /* now must do 9 (!) refresh or CBR commands before the first access */ +CBR_refresh1: + str r2, [r3] + subs r2, r2, #1 + bne CBR_refresh1 + + /* Step 8: Can re-enable DCACHE if it was disabled above (Skip on gumstix) */ + + /* Step 9: Enable SDRAM partitions */ + + ldr r3, =MDCNFG /* sdram config -- sdram enable */ + ldr r2, [r3] + orr r2, r2, #0x00000001 /* enable partition 0 only */ + str r2, [r3] /* write to MDCNFG */ + + /* Step 10: In systems containing SDRAM, write the MDMRS register to trigger an MRS command to all + * enabled banks of SDRAM. For each SDRAM partition pair that has one or both partitions + * enabled, this forces a pass through the MRS state and back to NOP. The CAS latency must be + * the only variable option and is derived from the value programmed in the + * MDCNFG:MDTC0,2 fields. The burst type is programmed to sequential and the length is set + * to four. */ + + ldr r3, =MDMRS /* write the MDMRS */ + ldr r2, =0x00020022 /* the writable bits will be written as a 0 */ + str r2, [r3] + + /* Step 11: (optional) Enable auto-power-down */ + + ldr r3, =MDREFR /* enable auto-power-down */ + ldr r2, [r3] + orr r2, r2, #0x00100000 /* set the APD bit */ + str r2, [r3] /* write to MDREFR */ + +end_of_memsetup: + mov pc, lr + diff -bBdurNP u-boot-1.1.1/board/gumstik/u-boot.lds u-boot-1.1.1-gum/board/gumstik/u-boot.lds --- u-boot-1.1.1/board/gumstik/u-boot.lds 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-1.1.1-gum/board/gumstik/u-boot.lds 2004-07-19 13:59:04.970844911 -0700 @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + board/gumstik/memsetup.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -bBdurNP u-boot-1.1.1/cpu/pxa/config.mk u-boot-1.1.1-gum/cpu/pxa/config.mk --- u-boot-1.1.1/cpu/pxa/config.mk 2003-05-23 05:36:21.000000000 -0700 +++ u-boot-1.1.1-gum/cpu/pxa/config.mk 2004-07-19 13:59:04.970844911 -0700 @@ -22,7 +22,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -mshort-load-bytes -msoft-float +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 -PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 +PLATFORM_CPPFLAGS += -mapcs-32 -mcpu=xscale -mtune=xscale diff -bBdurNP u-boot-1.1.1/cpu/pxa/mmc.c u-boot-1.1.1-gum/cpu/pxa/mmc.c --- u-boot-1.1.1/cpu/pxa/mmc.c 2003-10-15 16:53:52.000000000 -0700 +++ u-boot-1.1.1-gum/cpu/pxa/mmc.c 2004-07-19 13:59:04.971844735 -0700 @@ -26,10 +26,64 @@ #include #include #include + #include +// #define MMC_DEBUG +// #define debug printf + #ifdef CONFIG_MMC +void +mmc_print_stat() +{ + + int j,k=0; + short stat = MMC_STAT & MMC_STAT_ERRORS; + if (stat != 0) printf(""); else + for (j=1;j<256;j*=2) { + switch (stat & j) { + case (0x0001UL << 13): printf("END_CMD_RES. "); + k++; + break; + case (0x0001UL << 12): printf("PRG_DONE. "); + k++; + break; + case (0x0001UL << 11): printf("DATA_TRAN_DONE. "); + k++; + break; + case (0x0001UL << 8): printf("CLK_EN. "); + k++; + break; + case (0x0001UL << 7): printf("RECV_FIFO_FULL. "); + k++; + break; + case (0x0001UL << 6): printf("XMIT_FIFO_EMPTY. "); + k++; + break; + case (0x0001UL << 5): printf("RES_CRC_ERROR. "); + k++; + break; + case (0x0001UL << 4): printf("SPI_READ_ERROR_TOKEN. "); + k++; + break; + case (0x0001UL << 3): printf("CRC_READ_ERROR. "); + k++; + break; + case (0x0001UL << 2): printf("CRC_WRITE_ERROR. "); + k++; + break; + case (0x0001UL << 1): printf("TIME_OUT_RESPONSE. "); + k++; + break; + case (0x0001UL): printf("READ_TIME_OUT. "); + k++; + break; + default: break; + } + } +} + extern int fat_register_device(block_dev_desc_t *dev_desc, int part_no); @@ -58,7 +112,6 @@ ulong status; int words, i; - debug("mmc_cmd %x %x %x %x\n", cmd, argh, argl, cmdat); MMC_STRPCL = MMC_STRPCL_STOP_CLK; MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)); @@ -71,7 +124,9 @@ while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)); status = MMC_STAT; - debug("MMC status %x\n", status); +// printf("\n status> "); +// mmc_print_stat(); + if (status & MMC_STAT_TIME_OUT_RESPONSE) { return 0; @@ -100,15 +155,23 @@ resp[offset+1] = ((uchar *)&res_fifo)[1]; } #ifdef MMC_DEBUG + printf("\n results> "); for (i=0; i dst 0x%08x src 0x%08x len %d\n", (ulong)dst, src, len); argh = len >> 16; argl = len & 0xffff; @@ -132,20 +196,50 @@ resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); /* send read command */ - argh = src >> 16; - argl = src & 0xffff; +// printf("\nBLK READ> %d:",cmd); +// debug("\n block_read> 0x%02x 0x%02x 0x%02x 0x%02x", cmd, argh, argl, cmdat); +// resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); + MMC_STRPCL = MMC_STRPCL_STOP_CLK; + MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; + while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)); + MMC_RDTO = 0xffff; MMC_NOB = 1; MMC_BLKLEN = len; - resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, - MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); + MMC_CMD = MMC_CMD_READ_BLOCK; + MMC_ARGH = src >> 16; + MMC_ARGL = src & 0xffff; + MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN; + MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES; + MMC_STRPCL = MMC_STRPCL_START_CLK; + while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)); + status = MMC_STAT; +// printf(" "); +// printf("\n status> "); + mmc_print_stat(); + + if (status & MMC_STAT_TIME_OUT_RESPONSE) + { + return 0; + } MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ; + int c = 1; + while (len) { - if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) + c--; + + if (c==0) + { + while (c!=31) + { + if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) c=31; + } + } + { *dst++ = MMC_RXFIFO; len--; @@ -150,21 +244,32 @@ *dst++ = MMC_RXFIFO; len--; } + status = MMC_STAT; - if (status & MMC_STAT_ERRORS) + if (status & MMC_STAT_ERRORS ) { - printf("MMC_STAT error %lx\n", status); + printf("mmc_block_rd> MMC_STAT error 0x%08x\n", status & MMC_STAT_ERRORS ); return -1; } } + + debug("\n"); MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)); status = MMC_STAT; - if (status & MMC_STAT_ERRORS) + if (status & MMC_STAT_ERRORS ) { - printf("MMC_STAT error %lx\n", status); + printf("mmc_block_rd> MMC_STAT error 0x%08x\n", status & MMC_STAT_ERRORS); return -1; } + debug(" End block_read: "); + mmc_print_stat(); + debug("\n"); + +// *(origdst + DOS_PART_MAGIC_OFFSET) = 0x55; +// *(origdst + DOS_PART_MAGIC_OFFSET + 1) = 0xaa; + + return 0; } @@ -182,7 +287,7 @@ return 0; } - debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong)src, len); + debug("mmc_block_wr> dst 0x%08x src 0x%08x len %d\n", dst, (ulong)src, len); argh = len >> 16; argl = len & 0xffff; @@ -219,7 +324,7 @@ status = MMC_STAT; if (status & MMC_STAT_ERRORS) { - printf("MMC_STAT error %lx\n", status); + printf("MMC_STAT error 0x%08x\n", status); return -1; } } @@ -230,9 +335,10 @@ status = MMC_STAT; if (status & MMC_STAT_ERRORS) { - printf("MMC_STAT error %lx\n", status); + printf("MMC_STAT error 0x%08x\n", status); return -1; } + printf("MMC_STAT error 0x%08x\n", status); return 0; } @@ -252,10 +358,12 @@ if (!mmc_ready) { - printf("Please initial the MMC first\n"); + printf("Please initialize the MMC first\n"); return -1; } + debug(" mmc_read> MMC is ready.\n"); + mmc_block_size = MMC_BLOCK_SIZE; mmc_block_address = ~(mmc_block_size - 1); @@ -267,12 +375,12 @@ aligned_end = mmc_block_address & end; /* all block aligned accesses */ - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_read> src 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); if (part_start) { part_len = mmc_block_size - part_start; - debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_read> ps src 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { @@ -282,22 +390,22 @@ dst += part_len; src += part_len; } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_read> src 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) { - debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_read> al src 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) { return -1; } } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_read> src 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); if (part_end && src < end) { - debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_read> pe src 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { @@ -327,6 +435,8 @@ return -1; } + debug(" mmc_write> MMC is ready.\n"); + mmc_block_size = MMC_BLOCK_SIZE; mmc_block_address = ~(mmc_block_size - 1); @@ -338,12 +448,12 @@ aligned_end = mmc_block_address & end; /* all block aligned accesses */ - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug("src 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); if (part_start) { part_len = mmc_block_size - part_start; - debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_write> ps: src 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end); if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { @@ -357,22 +467,22 @@ dst += part_len; src += part_len; } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_write> src: 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) { - debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_write> al: src 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) { return -1; } } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_write> src: 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); if (part_end && dst < end) { - debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + debug(" mmc_write>pe src: 0x%08x dst 0x%08x end 0x%08x pstart 0x%08x pend 0x%08x astart 0x%08x aend 0x%08x\n", src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { @@ -411,6 +521,11 @@ set_GPIO_mode( GPIO6_MMCCLK_MD ); set_GPIO_mode( GPIO8_MMCCS0_MD ); #endif +#ifdef CONFIG_GUMSTIK + set_GPIO_mode( GPIO6_MMCCLK_MD ); + set_GPIO_mode( GPIO8_MMCCS0_MD ); +#endif + CKEN |= CKEN12_MMC; /* enable MMC unit clock */ mmc_csd.c_size = 0; @@ -420,13 +535,17 @@ MMC_SPI = MMC_SPI_DISABLE; /* reset */ - retries = 10; - resp = mmc_cmd(0, 0, 0, 0); + retries = 3; + + int i; + i=80; + while (i--) resp = mmc_cmd(0, 0, 0, 0); // Sends RESET command + resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3); while (retries-- && resp && !(resp[4] & 0x80)) { - debug("resp %x %x\n", resp[0], resp[1]); - udelay(50); + debug(" mmc_init> resp 0x%02x 0x%02x\n", resp[0], resp[1]); + udelay(20000); resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3); } @@ -438,30 +557,27 @@ mmc_cid_t *cid = (mmc_cid_t *)resp; if (verbose) { - printf("MMC found. Card desciption is:\n"); - printf("Manufacturer ID = %02x%02x%02x\n", - cid->id[0], cid->id[1], cid->id[2]); - printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); + printf("***********************************************\n"); + printf("* MMC found. Card desciption is: *\n"); + printf("* Manufacturer ID = %02x%02x%02x *\n", cid->id[2], cid->id[1], cid->id[0]); + printf("* HW/FW Revision = 0x%02x 0x%02x *\n",cid->hwrev, cid->fwrev); cid->hwrev = cid->fwrev = 0; /* null terminate string */ - printf("Product Name = %s\n",cid->name); - printf("Serial Number = %02x%02x%02x\n", - cid->sn[0], cid->sn[1], cid->sn[2]); - printf("Month = %d\n",cid->month); - printf("Year = %d\n",1997 + cid->year); + printf("* Product Name = %s *\n",cid->name); + printf("* Serial Number = %02x%02x%02x *\n", cid->sn[2], cid->sn[1], cid->sn[0]); + printf("* Month = %2d Year = %d *\n",cid->month,1997 + cid->year); + printf("***********************************************\n"); } /* fill in device description */ mmc_dev.if_type = IF_TYPE_MMC; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = 0; + mmc_dev.dev = 1; + mmc_dev.lun = 1; + mmc_dev.type = PART_TYPE_UNKNOWN; /* FIXME fill in the correct size (is set to 32MByte) */ - mmc_dev.blksz = 512; + mmc_dev.blksz = 0x200; mmc_dev.lba = 0x10000; - sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", - cid->id[0], cid->id[1], cid->id[2], - cid->sn[0], cid->sn[1], cid->sn[2]); + sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",cid->id[0], cid->id[1], cid->id[2],cid->sn[0], cid->sn[1], cid->sn[2]); sprintf(mmc_dev.product,"%s",cid->name); - sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); + sprintf(mmc_dev.revision,"0x%02x 0x%02x",cid->hwrev, cid->fwrev); mmc_dev.removable = 0; mmc_dev.block_read = mmc_bread; diff -bBdurNP u-boot-1.1.1/cpu/pxa/start.S u-boot-1.1.1-gum/cpu/pxa/start.S --- u-boot-1.1.1/cpu/pxa/start.S 2004-02-08 11:38:44.000000000 -0800 +++ u-boot-1.1.1-gum/cpu/pxa/start.S 2004-07-19 14:48:52.588013164 -0700 @@ -91,6 +91,7 @@ .word 0x0badc0de #endif +.space 0x800 /* JTAG install interrupt vectors over low memory in instruction cache */ /****************************************************************************/ /* */ @@ -104,6 +105,37 @@ orr r0,r0,#0x13 msr cpsr,r0 +/* This special code just unprotects all of flash, then erases it */ +// mov r0, #0x1f /* Loop over all blocks 0x1f-0x00*/ +//flash_wipe_main_loop: +// mov r1, r0, LSL #0x11 /* Convert bank number to start address */ +// mov r2, #0x60 /* Clear lock bit setup */ +// strh r2, [r1] +// nop +// mov r2, #0xd0 /* Clear lock bits confirm */ +// strh r2, [r1] +// nop +//flash_clear_wait_loop: +// ldrh r2, [r1] +// tst r2, #0x80 /* Check SR.7 */ +// bne flash_clear_wait_loop +// +// mov r2, #0x20 /* Block erase command */ +// strh r2, [r1] +// nop +// mov r2, #0xd0 /* Block erase confirm */ +// strh r2, [r1] +// nop +//flash_erase_wait_loop: +// ldrh r2, [r1] +// tst r2, #0x80 +// bne flash_clear_wait_loop +// +// teq r0, #0 +// subne r0, r0, #1 +// bne flash_wipe_main_loop +/* End of flash-nuking code */ + /* * we do sys-critical inits only at reboot, * not when booting from ram! @@ -113,10 +145,19 @@ #endif relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ + adrl r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ beq stack_setup + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifdef CONFIG_INIT_CRITICAL + bl cpu_init_crit + adrl r0, _start /* Reload r0 and r1 for relocation */ + ldr r1, _TEXT_BASE +#endif ldr r2, _armboot_start ldr r3, _bss_start diff -bBdurNP u-boot-1.1.1/fs/fat/fat.c u-boot-1.1.1-gum/fs/fat/fat.c --- u-boot-1.1.1/fs/fat/fat.c 2004-03-14 10:23:59.000000000 -0800 +++ u-boot-1.1.1-gum/fs/fat/fat.c 2004-07-19 13:59:04.972844558 -0700 @@ -78,11 +78,11 @@ printf ("** Can't read from device %d **\n", dev_desc->dev); return -1; } - if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || - buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { - /* no signature found */ - return -1; - } +// if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || +// buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { +// /* no signature found */ +// return -1; +// } if(!strncmp(&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { /* ok, we assume we are on a PBR only */ cur_part = 1; diff -bBdurNP u-boot-1.1.1/include/configs/gumstik.h u-boot-1.1.1-gum/include/configs/gumstik.h --- u-boot-1.1.1/include/configs/gumstik.h 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-1.1.1-gum/include/configs/gumstik.h 2004-07-20 16:14:28.494686977 -0700 @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2003 ETC s.r.o. +** +** Gumstik u-boot 1.0.0 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_PXA250 1 /* this is an PXA250 CPU */ +#define CONFIG_GUMSTIK 1 /* config for gumstik board */ +#define CONFIG_INIT_CRITICAL /* undef for developing */ +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ + + /* + * Select serial console configuration FFUART is default on G dev board +*/ + +#define CONFIG_FFUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SILENT_CONSOLE 1 + +/* + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. + */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + & ~CFG_CMD_FDC \ + & ~CFG_CMD_NET \ + | CFG_CMD_CACHE \ + | CFG_CMD_MMC \ + | CFG_CMD_FAT \ + | CFG_CMD_FLASH \ + | CFG_CMD_JFFS2 \ + ) + +/* + | CFG_HUSH_PARSER \ + & ~CFG_CMD_AUTOSCRIPT \ + & ~CFG_CMD_FDOS \ + & ~CFG_CMD_LOADS \ + & ~CFG_CMD_CONSOLE \ +*/ + + +#include + +/* + * Boot options. Setting delay to -1 stops autostart count down. + * NOTE: Sending parameters to kernel depends on kernel version and + * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept + * parameters at all! Do not get confused by them so. +*/ + +#define CONFIG_BOOTARGS "console=ttyS0,115200n8 root=1f02 rootfstype=jffs2 reboot=cold,hard" +#define CONFIG_BOOTCOMMAND "fsload a2000000 boot/uImage;bootm 0xa2000000" +#define CONFIG_BOOTDELAY 2 /* in seconds */ +#define CFG_PROMPT_HUSH_PS2 "HUSH> " + +/* +#define CONFIG_HARD_I2C +#define CONFIG_I2C_SPEED +#define CONFIG_I2C_SLAVE +*/ + +/* + * General options for u-boot. Modify to save memory foot print + */ + +#define CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "GUM> " /* prompt string */ +#define CFG_CBSIZE 512 /* console I/O buffer */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ +#define CFG_MAXARGS 16 /* max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ + + + +#define CFG_MEMTEST_START 0xa1000000 /* memtest test area */ +#define CFG_MEMTEST_END 0xa2000000 + + +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* core clock - register value 0x161 == 400MHz, 0x141 ==200MHz */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG 1 /* send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + + +/* + * Malloc pool need to host env + 128 Kb reserve for other allocations. + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) +#define CONFIG_STACKSIZE (120<<10) /* stack size */ + +#define CFG_GBL_DATA_SIZE 512 /* num bytes initial data */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ +#endif + +/* + * SDRAM Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB ( 2 chip ) */ +//#define PHYS_SDRAM_2 0xa4000000 /* SDRAM bank #2 */ +//#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +//#define PHYS_SDRAM_3 0xa8000000 /* SDRAM bank #3 */ +//#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +//#define PHYS_SDRAM_4 0xac000000 /* SDRAM bank #4 */ +//#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define CFG_DRAM_BASE PHYS_SDRAM_1 +#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE + +/* Uncomment used SDRAM chip */ +/*#define WEP_SDRAM_K4S281633*/ +/*#define WEP_SDRAM_K4S561633*/ + + +/* + * Configuration for FLASH memory [from wep250] + */ +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 32 /* number of sector in FLASH bank */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00400000 /* 04 MB */ +#define PHYS_FLASH_BANK_SIZE 0x00400000 /* 04 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */ + +/* This should be defined if CFI FLASH device is present. Actually benefit + is not so clear to me. In other words we can provide more informations + to user, but this expects more complex flash handling we do not provide + now.*/ + +#define CFG_FLASH_CFI +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * This is setting for JFFS2 support in u-boot. + * Right now there is no gain for user, but later on booting kernel might be + * possible. Consider using XIP kernel running from flash to save RAM + * footprint. + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + */ + +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 2 +#define CFG_JFFS2_NUM_BANKS 1 + +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xF0000000 + +/* + * Environment setup. Definitions of monitor location and size with + * definition of environment setup ends up in 2 possibilities. + * 1. Embedded environment - in u-boot code is space for environment + * 2. Environment is read from predefined sector of flash + * Right now we support 2. possiblity, but expecting no env placed + * on mentioned address right now. This also needs to provide whole + * sector for it - for us 256Kb is really waste of memory. U-boot uses + * default env. and until kernel parameters could be sent to kernel + * env. has no sense to us. + */ + +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ + +#define CFG_GPSR0_VAL 0xFFFFFFFF +#define CFG_GPSR1_VAL 0xFFFFFFFF +#define CFG_GPSR2_VAL 0xFFFFFFFF + +#define CFG_GPCR0_VAL 0x08022080 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 + +#define CFG_GPDR0_VAL 0xCD82A8F8 +#define CFG_GPDR1_VAL 0xFCFFAB80 +#define CFG_GPDR2_VAL 0x0001FFFF + +#define CFG_GAFR0_L_VAL 0x80000000 +#define CFG_GAFR0_U_VAL 0xA5254010 +#define CFG_GAFR1_L_VAL 0x599A9550 +#define CFG_GAFR1_U_VAL 0xAAA5AAAA +#define CFG_GAFR2_L_VAL 0xAAAAAAAA +#define CFG_GAFR2_U_VAL 0x00000002 + +#define CFG_PSSR_VAL 0x20 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_ENV_ADDR 0x20000 /* absolute address for now */ +#define CFG_ENV_SIZE 0x20000 /* env is writable now */ + +/* + * Well this has to be defined, but on the other hand it is used differently + * one may expect. For instance loadb command do not cares :-) + * So advice is - do not relay on this... + */ + +#define CFG_LOAD_ADDR 0xa3f00000 +#endif /* __CONFIG_H */ diff -bBdurNP u-boot-1.1.1/lib_arm/board.c u-boot-1.1.1-gum/lib_arm/board.c --- u-boot-1.1.1/lib_arm/board.c 2004-02-08 11:38:45.000000000 -0800 +++ u-boot-1.1.1-gum/lib_arm/board.c 2004-07-19 13:59:04.973844382 -0700 @@ -115,7 +115,7 @@ static int display_banner (void) { - printf ("\n\n%s\n\n", version_string); + printf ("\n\nWelcome to gumstix!\n%s\n\n", version_string); printf ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", _armboot_start, _bss_start, _bss_end); #ifdef CONFIG_MODEM_SUPPORT @@ -200,10 +200,10 @@ NULL, }; +DECLARE_GLOBAL_DATA_PTR; + void start_armboot (void) { - DECLARE_GLOBAL_DATA_PTR; - ulong size; init_fnc_t **init_fnc_ptr; char *s; diff -bBdurNP u-boot-1.1.1/board/gumstik/config.mk u-boot-1.1.1-new/board/gumstik/config.mk --- u-boot-1.1.1/board/gumstik/config.mk 2004-07-29 14:34:40.206035882 -0700 +++ u-boot-1.1.1-new/board/gumstik/config.mk 2004-07-29 13:55:32.865384865 -0700 @@ -8,4 +8,7 @@ # TEXT_BASE = 0xA3F00000 +ifeq ($(GUMSTIX_400MHZ),true) + PLATFORM_CPPFLAGS += -DCONFIG_GUMSTIX_CPUSPEED_400 +endif #TEXT_BASE = 0x00000000 diff -bBdurNP u-boot-1.1.1/include/configs/gumstik.h u-boot-1.1.1-new/include/configs/gumstik.h --- u-boot-1.1.1/include/configs/gumstik.h 2004-07-29 14:34:40.211035001 -0700 +++ u-boot-1.1.1-new/include/configs/gumstik.h 2004-07-29 13:45:59.134288840 -0700 @@ -101,7 +101,11 @@ #undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#ifdef CONFIG_GUMSTIX_CPUSPEED_400 #define CFG_CPUSPEED 0x161 /* core clock - register value 0x161 == 400MHz, 0x141 ==200MHz */ +#else +#define CFG_CPUSPEED 0x141 +#endif #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /*